Dr. Konstantinos Tatas Department of Electrical and Computer Engineering and Informatics Frederick University

Contact Information

Konstantinos Tatas

Assistant Professor

Department of Electrical and Computer Engineering and Informatics,

Frederick University,

7, Y. Frederickou Str.

Pallouriotisa, Nicosia 1036

Cyprus

Tel: +357 22394394(ext. 42212)

E-mail: com.tk@frederick.ac.cy

Office 212, Library Building

ResearchGate page

Teaching

FALL SEMESTER 2020:

ACOE101/ACSC110: Freshman Computer Engineering/Foundations of Computer Science: e-learning page

ACOE201: Computer Architecture: e-learning page

AELE210: Signals, Systems and Transforms: e-learning page

ACOE419/AEEE438:Digital VLSI Design: e-learning page

Research Interests

Design of Multiprocessor systems with NoC (Network-on-Chip) interconnect

Low-Power VLSI Design

Embedded System Design

Reconfigurable Architectures

Publications

Books:

1. K. Tatas , K. Siozios, D. Soudris, Axel Jantch, "Designing 2D and 3D Network-on-Chip Architectures", Springer, 2013

Book Chapters:

1. K. Tatas , K. Siozios, D. Soudris, "Survey of Fine-Grain Reconfigurable Architectures and Processors", in "Fine - and Coarse-Grain Reconfigurable Computing", Springer, 2007

2. D. Soudris, K. Tatas , K. Siozios, G. Koutroumpezis, S. Nikolaidis, S. Siskos, N. Vasiliadis, V. Kalenteridis, H. Pournara and I. Pappas, "AMDREL: A Novel Low-Energy FPGA Architecture and Supporting CAD Tool Design Flow" , in "Fine - and Coarse-Grain Reconfigurable Computing", Springer , 2007

Publications in International Journals:

1. Ahmad Al-Zoubi, Konstantinos Tatas and Costas Kyriacou, "Fuzzy classification of OpenCL programs targeting heterogeneous systems" , Journal of Intelligent & Fuzzy Systems, vol. 39, no. 5, pp. 7189-7202 IOS Press, 2020, DOI: 10.3233/JIFS-200616

2. K. Tatas and C. Chrysostomou, "Hardware Implementation of Dynamic Fuzzy Logic Based Routing in Network-on-Chip" , Microprocessors and Microsystems: Embedded Hardware Design, Special Issue on Euromicro Conference on Digital System Design , 2016, Elsevier, 2017

3. K. Tatas , K. Siozios , A. Bartzas , C. Kyriacou and D. Soudris, "A Novel Prototyping and Evaluation Framework for NoC-based MPSoC" , Networked Embedded Systems: Special Issue International Journal of Adaptive, Resilient and Autonomic Systems (IJARAS), IGI-Global , 2012

4. K. Tatas , C. Kyriacou, P. Evripidou, P. Trancoso and Stefan Wong, "Rapid Prototyping of the Data-Driven Chip Multiprocessor (D - CMP) using FPGAs" , Parallel Processing Letters, VOL 18; NUMB 2, pages 291-306, World Scientific , 2008

5. N. Kroupis, N. Zervas, M. Dasygenis, K. Tatas , A. Argyriou, D. Soudris and A. Thanailakis, "Behavioral-Level Performance and Power Exploration of Data-Intensive Applications Mapped on Programmable Processors" , VLSI Signal, Image and Video Processing, Springer, Volume 44 , Issue 1-2 (August 2006).

6. K. Siozios, G. Koutroumpezis, K. Tatas , N. Vasiliadis, V. Kalenteridis, H. Pournara, I. Pappas, D. Soudris, A. Thanailakis, S. Nikolaidis and S. Siskos, "A Novel FPGA Architecture and an Integrated Framework of CAD Tools for Implementing Applications" , in IEICE Transactions on Information and Systems "Special Issue on Recent Advances in Circuits and Systems", vol. E88-D, No. July 2005, pp.1369-1380 .

7. V. Kalenteridis, H. Pournara, K. Siozos, K. Tatas , I. Pappas, S. Nikolaidis, S.Siskos, D. J. Soudris and A. Thanailakis, "A Complete Platform and Toolset for System Implementation on Fine- Grain Reconfigurable Hardware" , special issue on FPGAs, Journal of Microprocessors and Microsystems, Elsevier Science.

8. K. Tatas , D. Soudris, D. Siomos and A. Thanailakis, "A Novel Division Algorithm and Architectures for Parallel and Sequential Processing" , Journal of Circuits, Systems, and Computers (JCSC), World Scientific, Volume 14, Number 1 , February 2005.

9. K. Tatas , G. Koutroumpezis, D. Soudris and A. Thanailakis, "Architecture Design of a Coarse-Grain Reconfigurable Multiply-Accumulate Unit for Data-Intensive Applications" , special issue on "VLSI System-On-Chip" of Integration, the VLSI Journal, Elsevier Science .

10. K. Tatas, D. Soudris and A. Thanailakis, "Memory Power Optimization of Hardware Implementations of Multimedia Applications onto FPGA Platforms", Issue 3 of 2004 of the Journal of Embedded Computing (JEC), Cambridge International Science Publishing .

11. K. Tatas, M. Dasygenis , N. Kroupis , A. Argyriou, D. Soudris, and A. Thanailakis, "Data memory power optimization and performance exploration of embedded systems for implementing motion estimation algorithms", in Real-Time Imaging, Vol. 9, No 6, December 2003, pp. 371-386, Special Issue on Software Engineering of Real-time Imaging Systems, Elsevier science

12. M. Dasygenis, N. Kroupis, K. Tatas , N. Zervas A. Argyriou, D. Soudris and A. Thanailakis, "A Methodology for Designing Low Power and High Performance Embedded Systems Executing Multimedia Kernels," in IEE Proceedings-Computer and Digital Techniques, Vol. 149, No.4, July 2002, pp. 164-172.

Publications in International Conferences and Workshops:

1. Ahmad Al-Zoubi and Konstantinos Tatas , “Rapid High-Level FPGA Resource Estimation for a Novel Heterogeneous Platform Scheduling Scheme”, 11th International Conference on Information and Communication Systems (ICICS 2020), April 7-9, 2020, Irbid, Jordan

2. A. Al-Zoubi, K. Tatas and C. Kyriacou, "Towards Dynamic Multi-task Scheduling of OpenCL Programs on Emerging CPU-GPU-FPGA Heterogeneous Platforms: a Fuzzy Logic Approach", Proc of 10th IEEE International Conference on Cloud Computing Technology and Science (CloudCom 2018), 10-13 December 2018, Nicosia, Cyprus

3. Konstantinos Tatas, "High-performance 3D NoC bufferless router with approximate priority comparison", 7th International Conference on Modern Circuits and Systems Technologies (MOCAST 2018), Thessaloniki, Greece, May 2018

4. A. Al-Zoubi, K. Tatas and C. Kyriacou, "Design space exploration of the KNN imputation on FPGA", in 7th International Conference on Modern Circuits and Systems Technologies (MOCAST), Thessaloniki, Greece, May 2018

5. K. Tatas, S. Savva and C. Kyriacou, "3DBUFFBLESS: A Novel Buffered-Bufferless Hybrid Router for 3D Networks-on-Chip", in 27th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS 2017), September 25-27, Thessaloniki, Greece

6. K. Tatas and C. Chrysostomou, "Adaptive Networks-on-Chip Routing with Fuzzy Logic Control", Proceedings of the Euromicro Conference on Digital System Design (DSD 2016), August 31 - September 2, 2016, Limassol, Cyprus

7. K. Tatas, S. Savva and C. Kyriacou, "Low-Cost Fault-Tolerant Routing for Regular Topology NoCs", in 21st IEEE International Conference on Electronics Circuits & Systems (ICECS 2014), Marseille, France, December 7-10, 2014

8. C. Chrysostomou, K. Tatas and A. R. Runcan, "A Dynamic Fuzzy Logic Based Routing Scheme for Bufferless NoCs", in 10th IEEE/IFIP International Conference on Embedded and Ubiquitous Computing, 5-7 December 2012, Paphos, Cyprus

9. K. Tatas and C. Chrysostomou, "A Novel Fuzzy Logic-Based Bufferless Routing Algorithm for Low-Power NoCs" in Proc. of DATICS-BCFIC 2012, Vilnius, Lithuania, 25-27 April 2012

10. K. Tatas, C. Kyriacou, K. Siozios, A. Bartzas and D. Soudris, "SYSMANTIC: A 3D NoC MPSoC Architecture Exploration and Implementation Framework", Design Automation and Test in Europe (DATE 2012), 3D Integration Workshop" Applications, Technology, Architecture, Design, Automation, and Test, 16/3/2012, Dresden, Germany

11. K. Tatas and C. Kyriacou, "Implementation of a Threaded Dataflow Multiprocessor using FPGAs", Proc. of the 6th International conference on Design & Technology of Integrated Systems in nanoscale era (DTIS'11), 6-8 April 2011, Athens, Greece

12. K. Tatas, C. Kyriacou, A. Bartzas, K. Siozios and D. Soudris, "A Novel NoC Architecture Framework for 3D Chip MPSoC Implementations", 3D Integration Workshop, Design Automation and Test in Europe (DATE 2010), 12/3/2010

13. K. Tatas, C. Kyriacou, G. Dekoulis, D. Demetriou, C. Avraam, and N. Christou, "Cache-Aware Network-on-Chip for Multiprocessor SoC", Proc. of SPIE Europe Microtechnologies for the new millennium, 4-6 May 2009, Dresden, Germany

14. K. Tatas and D. Soudris, "A Dynamically-Reconfigurable Motion Estimation IP Core for Adaptive Multimedia Systems", in Proc. of IFIP VLSI-SoC 2008, 13-15 October, 13-15 October 2008, Rhodes Island, Greece

15. K. Tatas, C. Kyriacou, S. Wong, P. Trancoso and P. Evripidou, "Rapid Prototyping of the Data-Driven Multithreading Chip-Multiprocessor using FPGAs", in Proc. of 2nd HiPEAC Reconfigurable Computing Workshop 2008, January 27, 2008, Goteborg, Sweden

16. K. Siozios, K. Tatas, D. Soudris, A. Thanailakis, "Platform-based FPGA architecture: designing high-performance and low-power routing structure for realizing DSP applications," Proceedings 13th Reconfigurable Architectures Workshop (RAW), pp. 10, April 25-26 2006, Rhodes Island, Greece

17. K. Siozios, K. Tatas, D. Soudris and A. Thanailakis, "A novel methodology for designing high-performance and low-energy FPGA routing architecture", Proceedings of the 2006 ACM/SIGDA 14th international symposium on Field programmable gate arrays, Monterey, California, USA, 2006, pp. 224

18. N. Kroupis, N. Zervas, M.Dasygnenis, K. Tatas, D. Soudris, and A Thanailakis, "High-Level Performance and Power Exploration of DSP Applications Realized on Programmable Processors," in Proc. of IEEE International Symposium on Signal Processing and Information Technology (ISSPIT), Athens, December 18 - 20, 2005.

19. K. Siozios, G. Koutroumpezis, K. Tatas, N. Vassiliadis, V. Kalenteridis, H. Pournara, I. Pappas, D. Soudris, S. Nikolaidis, S. Siskos and A. Thanailakis, "The AMDREL Project in Retrospective," in Proc. IFIP Inter. Conference in Very Large Scale Integration VLSI-SOC, October 17-19, 2005, Perth, Australia.

20. K. Siozios, K. Tatas, G. Koutroumpezis, D. Soudris and A. Thanailakis, "An Integrated Framework for Architecture-Level Exploration", 15th International Converence on Field-Programmable Logic and Applications (FPL), pp. 658-661, Aug. 24-26, 2005, Tampere, Finland.

21. K. Siozios, G. Koutroumpezis, K. Tatas, D. Soudris and A. Thanailakis, "DAGGER: A Novel Generic Methodology for FPGA Bitstream Generation and its Software Tool Implementation," in Proc. of RAW 2005,12th Reconfigurable Architectures Workshop Denver, Colorado, USA, April 4-5, 2005.

22. D. Soudris, S. Nikolaidis, S. Siskos, K. Tatas, K. Siozios, G. Koutroumpezis, N. Vasiliadis, V. Kalenteridis, H. Pournara, I. Pappas, and A. Thanailakis, "AMDREL: A NOVEL LOW-ENERGY FPGA ARCHITECTURE AND SUPPORTING CAD TOOL DESIGN FLOW", presentation in Design Contest of ASP-DAC 2005, Asia South Pacific Design Automation Conference, January 18-21, 2005, Shanghai, China.

23. K. Siozios, G. Koutroumpezis, K. Tatas, D. Soudris and A. Thanailakis, "A Novel FPGA Configuration Bistream Generation Algorithm and Tool Development", 14th International Conference on Field Programmable Logic and Applications (FPL 2004), Antwerp, Belgium, August 30- September 1, 2004, pp. 1116-1118.

24. E. Theochari, K. Tatas, D. Soudris and A. Thanailakis, "A Reusable IP FFT Core for DSP Applications", ISCAS 2004, Vancouver, May 23-26, 2004.

25. V. Kalenteridis, H. Pournara, K. Siozios, K. Tatas, I. Pappas, S. Nikolaidis, S.Siskos, D. J. Soudris and A. Thanailakis, "An Integrated FPGA Design Framework: Custom Designed FPGA Platform and Application Mapping Toolset Development", Reconfigurable Architectures Workshop (RAW) 2004, April 26-27, 2004, Santa Fe, New Mexico, USA.

26. K. Tatas, "VLSI Design of DSP Systems with Low Power Consumption", IFIP VLSI-SoC 2003, December 1-3, 2003, Darmstadt, Germany, pp. 459, Ph.D. forum.

27. M. Kesoulis, D. Soudris, C. Koukourlis, K. Tatas and A. Thanailakis, "Designing Low-Power Direct Digital Frequency Synthesizers", IFIP VLSI-SoC 2003, December 1-3, 2003, Darmstadt, Germany, pp. 105-110.

28. K. Tatas, K. Siozios, N. Vasiliadis, D. Soudris, S. Nikolaidis, S. Siskos, Adonios Thanailakis: "A Novel Embedded FPGA Architecture with Complete Tool Implementation Flow". PATMOS 2003, September 10-12, 2003, Torino, Italy, pp. 607-616

29. K. Tatas, K. Siozios, D. Soudris, A. Thanailakis, K. Masselos, K. Potamianos, S. Blionas: "Power Optimization Methodology for Multimedia Applications Implementation on Reconfigurable Platforms". PATMOS 2003, September 10-12, 2003, Torino, Italy, pp. 430-439

30. K. Tatas, D. Soudris, K. Siozios and A. Thanailakis, "Memory Power Optimization of Hardware Implementations of Multimedia Applications", 13th International Conference on Field Programmable Logic and Applications (FPL 2003), Lisbon - Portugal, September 1-3, 2003.

31. D. Soudris, K. Sgouropoulos, K. Tatas, V. Pavlidis and A. Thanailakis, "A Methodology for Implementing FIR Filters and CAD Tool Development for Designing RNS-Based Systems", in IEEE International Symposium on Circuits and Systems (ISCAS 2003), Bangkok, Thailand, May 25-28, 2003, pp. V-129--132.

32. D. Soudris, K. Masselos, S. Blionas, S. Siskos, S. Nikolaidis and K. Tatas, "AMDREL: On Designing Reconfigurable Embedded Structures for the Future Reconfigurable SoC for Wireless Communication Applications", Proc. of SSCS, 2002.

33. D. Soudris, M. Dasygenis, K. Mitroglou, K. Tatas and A. Thanailakis, "A Full-Adder Based Methodology for Scaling Operation in Residue Number System", Proc. of 9th IEEE International Conference on Electronics, Circuits and Systems (ICECS 2002), September 15-18, 2002, Dubrovnik Croatia, pp. 891-894.

34. K. Tatas, D.J. Soudris, D. Siomos, M. Dasygenis and A. Thanailakis, "A Novel Division Algorithm for Parallel and Sequential Processing", Proc. of 9th IEEE International Conference on Electronics, Circuits and Systems (ICECS 2002), September 15-18, 2002, Dubrovnik Croatia, pp. 553-556.

35. G. Koutroumpezis, K. Tatas, D. Soudris, S. Blionas, K. Masselos, and A. Thanailakis, "Architecture Design of a Reconfigurable Multiplier for Flexible Corse-grain Implementations", Proc. of 12th International Conference on Field Programmable Logic and Applications (FPL), September 2-4, 2002 , Montpellier (La Grande-Motte), France.

36. N. Kroupis, M. Dasygenis, A. Argyriou, K. Tatas, D. Soudris, A. Thanailakis and N. Zervas, "Power, Performance and Area Exploration of block matching algorithms mapped on programmable processors", in IEEE 2001 International Conference on Image Processing (ICIP), Thessaloniki, Greece, Oct 2001, pp. 728-731.

37. K. Tatas, M. Dasygenis, A. Argyriou, N. Kroupis, D. Soudris and A. Thanailakis, "Address Bus Power Exploration in Programmable Processors for Realization of Multimedia Applications", IEEE International Workshop on Power and Timing Modelling, Optimization and Simulation (PATMOS), Yverdon-Les-Bains, Switzerland, September 2001, pp. 10.2.1 - 10.2.10.

38. M. Dasigenis, N. Kroupis, A. Argyriou, K. Tatas, D. Soudris, N. D. Zervas and "Data And Instruction Memory Exploration Of Embedded Systems For Multimedia Applications", in proceedings of IEEE 2001 International Conference on Acoustics, Speech, and Signal Processing (ICASSP2001), Salt Lake City, Utah, May 2001.

39. 55. M. Dasygenis, N. Kroupis, A. Argyriou, K. Tatas, D. Soudris and N. Zervas, “A memory management approach for efficient implementation of multimedia kernels on programmable architectures”, in IEEE Computer Society Annual Workshop on VLSI (WVLSI), Orlando Florida, USA, April 19-20, 2001, pp. 171-176.

40. K.Tatas, A. Argyriou, M. Dasigenis, N. Zervas, and D. Soudris, “Memory Hierarchy Optimization of Multimedia Applications on Programmable Embedded Cores,” in Proc. of IEEE 2001 International Symposium on Quality Electronic Design (ISQED), March 26-28, 2001, San Jose, California, USA, pp. 456-461.

41. A. Argyriou, M. Dasygenis, K. Tatas, N. Zervas, and D. Soudris, “Data-Reuse Exploration of Multimedia Applications on Programmable Processor Cores”, Proc of IEEE International Conference on Design of Circuits and Integrated Systems (DCIS), Montpellier, France, pp.651-656, November 2000.

42. D. Soudris, K. Tatas and A. Thanailakis, “A Novel Algorithm for Integer Division”, Proc of IEEE International Conference on Design of Circuits and Integrated Systems (DCIS), Montpellier, France, pp.193-198, November 2000.

43. D. Soudris, N. D. Zervas, A. Argyriou, M. Dasygenis, K. Tatas, C. Goutis, A. Thanailakis, “Data-Reuse and Parallel Embedded Architectures for Low-Power, Real-Time Multimedia Applications”, Proc of IEEE International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS), Göttingen, Germany, pp. 243- 254, Sept. 2000.

Publications in National Conferences and Workshops:

1. Ι. Pappas, N. Vassiliadis, V. Kalenteridis, H. Pournara, S. Nikolaidis, S.Siskos, K. Siozios, G. Koutroumpezis, K. Tatas, D. J. Soudris, A. Thanailakis, “Fine-Grain Reconfigurable Platform: FPGA Hardware Design and Software Toolset Development,” in Proceedings of Microelectronics Microsystems and Nanotechnology, between 14 and 17 November 2004, Greece.

Research Projects

“iPONICS: Smart Off-Grid System for Sustainable Hydroponics", Cypus Research and Innovation Foundation, 2019-2021 (webpage)

“SYSMANTIC: SYStematic design of 3D Multicore Architectures with NeTwork-on-chIp Communication", Cypus Research Promotion Foundation, 2010 – 2012 (webpage)

"DDM-CMP: Data Driven Multithreading on a Chip Multiprocessor, Development and Implementation", Cypus Research Promotion Foundation, 2005-2008

“AMDREL: "Architectures and Methodologies for Dynamic REconfigurable Logic”, European Commission - 5th IST Framework, 2002 – 2005 (webpage)