Welcome to the web page of Dr. Konstantinos Tatas
                                                          Assistant Professor
                                                          Department of Computer Science and Engineering
                                                          E-mail: com.tk@frederick.ac.cy
                                                          Office 116, Library Building





Teaching





Research


Research interests:
  •       Design of Multiprocessor systems with NoC (Network-on-Chip) interconnect
  •       Low-Power VLSI Design
  •       Multimedia System Design and VLSI Implementation
  •       Embedded System Design
  •       Reconfigurable Architectures


Publications

Books:
  1. K. Tatas, K. Siozios, D. Soudris, Axel Jantch, “Designing 2D and 3D Network-on-Chip Architectures”, Springer, 2013

Book Chapters:
  1. K. Tatas, K. Siozios, D. Soudris, “Survey of Fine-Grain Reconfigurable Architectures and Processors”, in “Fine – and Coarse-Grain Reconfigurable Computing. Editors: S. Vassiliadis and D. Soudris, Springer,  2007
  2. D. Soudris, K. Tatas, K. Siozios, G. Koutroumpezis, S. Nikolaidis, S. Siskos, N. Vasiliadis, V. Kalenteridis, H. Pournara and I. Pappas, “AMDREL: A Novel Low-Energy FPGA Architecture and Supporting CAD Tool Design Flow”, in “Fine – and Coarse-Grain Reconfigurable Computing”, Editors: S. Vassiliadis and D. Soudris, Springer, 2007

Publications in International Journals:
  1. M. Dasygenis, N. Kroupis, K. Tatas, N. Zervas A. Argyriou, D. Soudris and A. Thanailakis, “A Methodology for Designing Low Power and High Performance Embedded Systems Executing Multimedia  Kernels,” in IEE Proceedings-Computer and Digital Techniques, Vol. 149, No.4, July 2002, pp. 164-172.
  2. K. Tatas , M. Dasygenis , N. Kroupis , A. Argyriou, D. Soudris, and A. Thanailakis, “Data memory power optimization and performance exploration of embedded systems for implementing motion estimation algorithms”, in Real-Time Imaging, Vol. 9, No 6, December 2003, pp. 371-386, Special Issue on Software Engineering of Real-time Imaging Systems, Elsevier science.
  3. K. Tatas, D. Soudris and A. Thanailakis, “Memory Power Optimization of Hardware Implementations of Multimedia Applications onto FPGA Platforms”, Issue 3 of 2004 of the Journal of Embedded Computing (JEC), Cambridge International Science Publishing.
  4. K. Tatas, G. Koutroumpezis, D. Soudris and A. Thanailakis, “Architecture Design of a Coarse-Grain Reconfigurable Multiply-Accumulate Unit for Data-Intensive Applications”, special issue on "VLSI System-On-Chip" of Integration, the VLSI Journal, Elsevier Science.
  5. K. Tatas, D. Soudris, D. Siomos and A. Thanailakis, “A Novel Division Algorithm and Architectures for Parallel and Sequential Processing”, Journal of Circuits, Systems, and Computers (JCSC), World Scientific, Volume 14, Number 1, February 2005.
  6. V. Kalenteridis, H. Pournara, K. Siozos, K. Tatas, I. Pappas, S. Nikolaidis, S.Siskos, D. J. Soudris and A. Thanailakis, “A Complete Platform and Toolset for System Implementation on Fine- Grain Reconfigurable Hardware”, special issue on FPGAs, Journal of Microprocessors and Microsystems, Elsevier Science.
  7. K. Siozios, G. Koutroumpezis, K. Tatas, N. Vasiliadis, V. Kalenteridis, H. Pournara, I. Pappas, D. Soudris, A. Thanailakis, S. Nikolaidis and S. Siskos, “A Novel FPGA Architecture and an Integrated Framework of CAD Tools for Implementing Applications”, in  IEICE Transactions on Information and Systems "Special Issue on Recent Advances in Circuits and Systems", vol. E88-D, No. July 2005, pp.1369-1380.
  8. N. Kroupis, N. Zervas, M. Dasygenis, K. Tatas, A. Argyriou, D. Soudris and A. Thanailakis: “Behavioral-Level Performance and Power Exploration of Data-Intensive Applications Mapped on Programmable Processors”, VLSI Signal, Image and Video Processing, Springer, Volume 44 ,  Issue 1-2 (August 2006).
  9. K. Tatas, C. Kyriacou, P. Evripidou, P. Trancoso and Stefan Wong, “Rapid Prototyping of the Data-Driven Chip Multiprocessor (D - CMP) using FPGAs”, Parallel Processing Letters, VOL 18; NUMB 2, pages 291-306, 2008, World Scientific
  10. K. Tatas , K. Siozios , A. Bartzas , C. Kyriacou  and D. Soudris, “A Novel Prototyping and Evaluation Framework for NoC-based MPSoC”, accepted for publication in       Networked Embedded Systems: Special Issue International Journal of Adaptive, Resilient and Autonomic Systems (IJARAS), IGI-Global, 2012
  11. Konstantinos Tatas, "A Novel Source-Distributed Hybrid Routing Framework for Regular Topology Networks-on-Chip", accepted with minor revision in the Journal of Circuits, Systems, and Computers,  World Scientific Publishing

Publications in International Conference Proceedings:
  1. D. Soudris, N. D. Zervas, A. Argyriou, M. Dasygenis, K. Tatas, C. Goutis, A. Thanailakis, “Data-Reuse and Parallel Embedded Architectures for Low-Power, Real-Time Multimedia Applications”, IEEE International Workshop on Power and Timing Modeling, Optimization and Simulation  (PATMOS), Göttingen, Germany, pp. 243- 254, Sept. 2000.
  2. A. Argyriou, M. Dasygenis, K. Tatas, N. Zervas, and D. Soudris, “Data-Reuse Exploration of Multimedia Applications on Programmable Processor Cores”, IEEE International Conference on Design of Circuits and Integrated Systems (DCIS), Montpellier, France, pp.651-656, November 2000.
  3. D. Soudris, K. Tatas and A. Thanailakis, “A Novel Algorithm for Integer Division”, IEEE International Conference on Design of Circuits and Integrated Systems (DCIS), Montpellier, France, pp.193-198, November 2000.
  4. K.Tatas, A. Argyriou, M. Dasigenis, N. Zervas, and D. Soudris, “Memory Hierarchy Optimization of Multimedia Applications on Programmable Embedded Cores,” in Proc. of IEEE 2001 International Symposium on Quality Electronic Design (ISQED), March 26-28, 2001, San Jose, California, USA, pp. 456-461.
  5. M. Dasygenis, N. Kroupis, A. Argyriou, K. Tatas, D. Soudris and N. Zervas: “A memory management approach for efficient implementation of multimedia kernels on programmable architectures”, in IEEE Computer Society Annual Workshop on VLSI (WVLSI), Orlando Florida, USA, April 19-20, 2001,  pp. 171-176.
  6. M. Dasigenis, N. Kroupis, A. Argyriou, K. Tatas, D. Soudris, N. D. Zervas and “Data And Instruction Memory Exploration Of Embedded Systems For Multimedia Applications”, in proceedings of IEEE 2001 International Conference on Acoustics, Speech, and Signal Processing (ICASSP’2001), Salt Lake City, Utah, May 2001.
  7. K. Tatas, M. Dasygenis, A. Argyriou, N. Kroupis, D. Soudris and A. Thanailakis, “Address Bus Power Exploration in Programmable Processors for Realization of Multimedia Applications”, IEEE International Workshop on Power and Timing Modelling, Optimization and Simulation (PATMOS), Yverdon-Les-Bains, Switzerland, September 2001, pp. 10.2.1 – 10.2.10.
  8. N. Kroupis, M. Dasygenis, A. Argyriou, K. Tatas, D. Soudris, A.  Thanailakis and N. Zervas, “Power, Performance and Area Exploration of block matching algorithms mapped on programmable processors”, in IEEE 2001 International Conference on Image Processing (ICIP), Thessaloniki, Greece, Oct 2001, pp. 728-731.
  9. G. Koutroumpezis, K. Tatas, D. Soudris, S. Blionas, K. Masselos, and A. Thanailakis, “Architecture Design of a Reconfigurable Multiplier for Flexible Corse-grain Implementations“, Proc. of 12th International Conference on Field Programmable Logic and Applications (FPL), September 2-4, 2002 , Montpellier (La Grande-Motte) – France.
  10. K. Tatas, D.J. Soudris, D. Siomos, M. Dasygenis and A. Thanailakis, “A Novel Division Algorithm for Parallel and Sequential Processing”, Proc. of 9th IEEE International Conference on Electronics, Circuits and Systems (ICECS 2002), September 15-18, 2002, Dubrovnik Croatia, pp. 553-556.
  11. D. Soudris, M. Dasygenis, K. Mitroglou, K. Tatas and A. Thanailakis, “A Full-Adder Based Methodology for Scaling Operation in Residue Number System”, Proc. of 9th IEEE International Conference on Electronics, Circuits and Systems (ICECS 2002), September 15-18, 2002, Dubrovnik Croatia, pp. 891-894.
  12. D. Soudris, K. Masselos, S. Blionas, S. Siskos, S. Nikolaidis and K. TatasAMDREL: On Designing Reconfigurable Embedded Structures for the Future Reconfigurable SoC for Wireless Communication Applications”, Proc. of SSCS, 2002.
  13. D. Soudris, K. Sgouropoulos, K. Tatas, V. Pavlidis and A. Thanailakis, “A Methodology for Implementing FIR Filters and CAD Tool Development for Designing RNS-Based Systems,” in IEEE International Symposium on Circuits and Systems (ISCAS 2003), Bangkok, Thailand, May 25-28, 2003, pp. V-129--132.
  14. K. Tatas, D. Soudris, K. Siozios and A. Thanailakis, "Memory Power Optimization of Hardware Implementations of Multimedia Applications”, 13th International Conference on Field Programmable Logic and Applications (FPL 2003), Lisbon - Portugal, September 1-3, 2003.
  15. K. Tatas, K. Siozios, D. Soudris, A. Thanailakis, K. Masselos, K. Potamianos, S. Blionas: “Power Optimization Methodology for Multimedia Applications Implementation on Reconfigurable Platforms”. PATMOS 2003, September 10-12, 2003, Torino, Italy, pp. 430-439
  16. K. Tatas, K. Siozios, N. Vasiliadis, D. Soudris, S. Nikolaidis, S. Siskos, Adonios Thanailakis: “A Novel Embedded FPGA Architecture with Complete Tool Implementation Flow”. PATMOS 2003, September 10-12, 2003, Torino, Italy, pp. 607-616
  17. M. Kesoulis, D. Soudris, C. Koukourlis, K. Tatas and A. Thanailakis, “Designing Low-Power Direct Digital Frequency Synthesizers”, VLSI-SoC 2003, December 1-3, 2003, Darmstadt, Germany, pp. 105-110.
  18. K. Tatas, “VLSI Design of DSP Systems with Low Power Consumption”, VLSI-SoC 2003, December 1-3, 2003, Darmstadt, Germany, pp. 459, Ph.D. forum.
  19. V. Kalenteridis, H. Pournara, K. Siozios,  K. Tatas, I. Pappas, S. Nikolaidis, S.Siskos, D. J. Soudris and A. Thanailakis, “An Integrated FPGA Design Framework: Custom Designed FPGA Platform and Application Mapping  Toolset Development”, Reconfigurable Architectures Workshop (RAW) 2004, April 26-27, 2004, Santa Fe, New Mexico, USA.
  20. E. Theochari, K. Tatas, D. Soudris and A. Thanailakis, "A Reusable IP FFT Core for DSP Applications“, ISCAS 2004, Vancouver, May 23-26, 2004.
  21. K. Siozios, G. Koutroumpezis, K. Tatas, D. Soudris and A. Thanailakis, “A Novel FPGA Configuration Bistream Generation Algorithm and Tool Development”, 14th International Conference on Field Programmable Logic and Applications (FPL 2004), Antwerp, Belgium, August 30- September 1, 2004, pp. 1116-1118.
  22. D. Soudris, S. Nikolaidis, S. Siskos, K. Tatas, K. Siozios, G. Koutroumpezis, N. Vasiliadis, V. Kalenteridis, H. Pournara, I. Pappas, and A. Thanailakis, “AMDREL: A NOVEL LOW-ENERGY FPGA ARCHITECTURE AND SUPPORTING CAD TOOL DESIGN FLOW,” accepted for presentation in Design Contest of ASP-DAC 2005, Asia South Pacific – Design Automation Conference, January 18-21, 2005, Shanghai, China.
  23. K. Siozios, G. Koutroumpezis, K. Tatas, D. Soudris and A. Thanailakis, DAGGER: “A Novel Generic Methodology for FPGA Bitstream Generation and its Software Tool Implementation,” in Proc. of RAW 2005,12th Reconfigurable Architectures Workshop Denver, Colorado, USA, April 4-5, 2005.
  24. K. Siozios, K. Tatas, G. Koutroumpezis, D. Soudris and A. Thanailakis, “An Integrated Framework for Architecture-Level Exploration”, 15th International Converence on Field-Programmable Logic and Applications (FPL), pp. 658-661, Aug. 24-26, 2005, Tampere, Finland.
  25. K. Siozios, G. Koutroumpezis, K. Tatas, N. Vassiliadis, V. Kalenteridis, H. Pournara, I. Pappas, D. Soudris, S. Nikolaidis, S. Siskos and A. Thanailakis, "The AMDREL Project in Retrospective," accepted for presentation in in Proc. IFIP Inter. Conference in Very Large Scale Integration VLSI-SOC, October 17-19, 2005, Perth, Australia.
  26. N. Kroupis, N. Zervas, M.Dasygnenis, K. Tatas, D. Soudris, and A Thanailakis "High-Level Performance and Power Exploration of DSP Applications Realized on Programmable Processors," accepted for presentation in IEEE International Symposium on Signal Processing and Information Technology (ISSPIT), Athens, December 18 - 20, 2005.
  27. K. Siozios, K. Tatas, D. Soudris and A. Thanailakis, “A novel methodology for designing high-performance and low-energy FPGA routing architecture, Proceedings of the 2006 ACM/SIGDA 14th international symposium on Field programmable gate arrays, Monterey, California, USA, 2006, pp. 224
  28. K. Siozios, K. Tatas, D. Soudris, A. Thanailakis, "Platform-based FPGA architecture: designing high-performance and low-power routing structure for realizing DSP applications," Proceedings 13th Reconfigurable Architectures Workshop (RAW), pp. 10, April 25-26 2006, Rhodes Island, Greece
  29. K. Tatas, C. Kyriacou, S. Wong, P. Trancoso and P. Evripidou, “Rapid Prototyping of the Data-Driven Multithreading Chip-Multiprocessor using FPGAs”, 2nd HiPEAC Reconfigurable Computing Workshop 2008, January 27, 2008, Göteborg, Sweden
  30. K. Tatas and D. Soudris, “A Dynamically-Reconfigurable Motion Estimation IP Core for Adaptive Multimedia Systems”, VLSI-SoC 2008, 13-15 October, 13-15 October 2008, Rhodes Island, Greece
  31. K. Tatas, C. Kyriacou, G. Dekoulis, D. Demetriou, C. Avraam, and N. Christou, “Cache-Aware Network-on-Chip for Multiprocessor SoC”, in SPIE Europe Microtechnologies for the new millennium, 4-6 May 2009, Dresden, Germany
  32. K. Tatas, C. Kyriacou, A. Bartzas, K. Siozios and D. Soudris, “A Novel NoC Architecture Framework for 3D Chip MPSoC Implementations”, accepted for presentation in the 3D Integration Workshop, Design Automation and Test in Europe (DATE 2010), 12/3/2010
  33. K. Tatas and C. Kyriacou, “Implementation of a Threaded Dataflow Multiprocessor using FPGAs”, Proc. of the 6th International conference on Design & Technology of Integrated Systems in nanoscale era (DTIS'11), 6-8 April 2011, Athens, Greece
  34. K. Tatas, C. Kyriacou, K. Siozios, A. Bartzas and D. Soudris, "SYSMANTIC: A 3D NoC MPSoC Architecture Exploration and Implementation Framework", Design Automation and Test in Europe (DATE 2012), 3D Integration Workshop – Applications, Technology, Architecture, Design, Automation, and Test, 16/3/2012, Dresden, Germany
  35. K. Tatas and C. Chrysostomou, "A Novel Fuzzy Logic-Based Bufferless Routing Algorithm for Low-Power NoCs" in Proc. of DATICS-BCFIC 2012, Vilnius, Lithuania, 25-27 April 2012
  36. C. Chrysostomou, K. Tatas and A. R. Runcan, “A Dynamic Fuzzy Logic Based Routing Scheme for Bufferless NoCs”, accepted as full paper to the 10th IEEE/IFIP International Conference on Embedded and Ubiquitous Computing, 5-7 December 2012, Paphos, Cyprus
  37. K. Tatas, S. Savva and C. Kyriacou, "Low-Cost Fault-Tolerant Routing for Regular Topology NoCs",  21st IEEE International Conference on Electronics Circuits & Systems (ICECS 2014), Marseille, France, December 7-10, 2014

Publications in National (Greek) Conference Proceedings:
  1. Pappas, N. Vassiliadis, V. Kalenteridis, H. Pournara, S. Nikolaidis, S.Siskos, K. Siozios, G. Koutroumpezis, K. Tatas, D. J. Soudris, A. Thanailakis, “Fine-Grain Reconfigurable Platform: FPGA Hardware Design and Software Toolset Development,” in Proceedings of Microelectronics, Microsystems and Nanotechnology, 14-17 November 2004, Greece.